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Text File  |  1987-01-02  |  2KB  |  67 lines
  1.  
  2.  
  3.  
  4.  
  5.  
  6.  
  7.                                     Improvements
  8.  
  9.             Version 2.0:
  10.  
  11.                            The gates DELAYH, DELAYL, and XNOR were added
  12.  
  13.                            The options  GATEDELAY,  WIDTH,  and  INITIAL
  14.                            were added
  15.  
  16.                            The TIME and FANOUT options were improved
  17.  
  18.                            Error detection  was improved,  as errors  in
  19.                            either a  circuit descriptor or chip descrip-
  20.                            tor could  cause version 1.0 to hang, requir-
  21.                            ing a  control-break  to  stop  the  program.
  22.                            Now, version 2.0 detects those situations and
  23.                            aborts.
  24.  
  25.                            Simulation time was improved by altering some
  26.                            of the  data structures  and simplifying  the
  27.                            chip equations  when constant  highs or  lows
  28.                            are present
  29.  
  30.                            More chip descriptors were added.
  31.  
  32.                            
  33.  
  34.             Version 2.1:
  35.  
  36.                            Long sequences  of 1's  and 0's  in DATA  and
  37.                            CLOCK sources  can now  be represented by re-
  38.                            peat counts  (e.g. 111111  can  be  typed  as
  39.                            (6*1) ).
  40.  
  41.                            The maximum delay is now 32,767 time units, a
  42.                            great increase  over the old limit of 32 time
  43.                            units.
  44.  
  45.                            
  46.             ************************************************************
  47.             ************************************************************
  48.  
  49.                                 Planned improvements
  50.  
  51.             RAM chip  implementation.   Attempting to use RAM devices in
  52.                  LOGSIM (still)  is a  pain, and  is cautioned  against.
  53.                  DON'T, unless  you absolutely have to.  It's just hard,
  54.                  not dangerous  to code  a RAM  chip.   A future version
  55.                  will have a simple facility for simulating RAM devices.
  56.  
  57.             More memory.   LOGSIM  currently can  only use less than 64K
  58.                  for your  circuit.   In the future, this will expand to
  59.                  the limits of your PC's memory.
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